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? semiconductor components industries, llc, 2016 july, 2016 ? rev. 4 1 publication order number: ncl30060/d ncl30060 high pf offline single stage led driver with high voltage startup the ncl30060 is a switch mode power supply controller intended for low to medium power single stage power factor (pf) corrected led drivers. it employs a constant on?time control method to ensure near unity power factor across a wide range of input voltages and output power. it can be used for isolated flyback as well as buck topologies. the device offers a suite of robust protection features to ensure safe operation under a range of fault conditions. version ncl30060b2 is intended for constant voltage (cv) regulated output drivers where a dc?dc converter or linear regulator in the second stage controls the current to the leds so the output short circuit protection detector function has been disabled. features ? built?in high voltage start?up circuit ? direct opto?coupler feedback connection ? constant on?time pwm control ? quasi?resonant switching ? low operating current (1.6 ma typical) ? source 250 ma / sink 400 ma totem pole gate driver ? integrated 12 v (typ) gate drive clamp ? frequency dithering for reduced emi profile ? enable/disable function ? dynamic self?supply (dss) operation ? operating t j from ?40 c to 105 c ? maximum on time protection ? integrated brown?out ? overvoltage protection ? cycle?by?cycle overcurrent protection ? output winding short?circuit protection ? thermal shutdown ? these devices are pb?free, halogen free/bfr free and are rohs compliant typical applications ? led lighting soic?7 case 751u marking diagram www. onsemi.com l0060xx alyw 1 8 l0060xx = specific device code xx = a, b, b1, b2 a = assembly location l = wafer lot y = year w = work week = pb?free package see detailed ordering and shipping information on page 14 o f this data sheet. ordering information 18 5 3 4 (top view) fb rt hv pin connections 6 2 cs/zcd gnd drv vcc (note: microdot may be in either location)
ncl30060 www. onsemi.com 2 figure 1. ncl30060 typical application diagram ncl30060 rt fb cs vcc u1 hv ncp4328a u3 emi filter fbc vcc gnd isns vsns ccomp1 rvcc1 rt cy dzcd cvcc1 line m1 rcs cclamp rvout2 cvcc ris + cout led cathode ris1 dout rvout1 ccomp2 led anode rclamp neutral rzcd u2 1 2 3 4 rcomp2 cfb dvcc1 rsense cin dhv dclamp dvcc ro gnd drv
ncl30060 www. onsemi.com 3 figure 2. ncl30060 internal functional block diagram + ? internal reference thermal shutdown uvlo vcc_ok hv vcc pwm comparator max on time comparator rt current mirror ? + on time ramp drv fb offset short winding comparator + ? cs/zcd peak current comparator zcd comparator disable drv reset uvlo edge detector zcd blanking time + ? + ? ovp comparator + ? blanking (fault_ovp) drv selector ilim2, ovp ramp modulation gnd r s q q uvlo clamp drv tshdn tshdn vcc management central logic auto?restart fault control active fb active counter reset count counter reset count active ilim2 open rt pin re?start drv hv(high) drv v on?time brown?out detection ?hv tran bo_nok + ? active active short circuit detector drv integration pulse drv max on?time clamp drv + ? v dd2 v ton(max) v dd delay t shdn(delay) delay t disable(blank) / t enable(blank) v cc v dd2 v cc(on) / v cc(off) / v cc(reset) / v cc(ruvlo) / v cc(ovp) v ilim1 v ilim2 v ovp maximum off?time detector t off(max) v cc reset dominant latch v cc t off1,2 timer edge detector leb t cs(leb2) leb t cs(leb1) rt disable comparator i rt(disable) * r cs rt enable comparator v rt(enable) t on(mod) r cs i rt startup control t int v prt f mod v zcd i start selector
ncl30060 www. onsemi.com 4 table 1. ncl30060 pin function description pin no pin name pin description 1 fb feedback input. the fb pin is the control input to the pwm comparator. a voltage level controlled by the feedback loop on this pin is compared to the internal ramp establishing power switch on time. 2 cs/zcd current sense and zero current detection. the cs input is used to sense the instantaneous switch cur- rent in the external power switch during switch on time. a fast?responding high threshold level for short circuit detection is provided along with a longer blanking time at lower level for overload conditions. dur- ing switch off time, this pin monitors the bias winding to detect transformer demagnetization. when stored energy is depleted the gate drive turns on the power switch initiating the next cycle. this pin also detects overvoltage conditions through the bias winding. a blanking time prevents false overvoltage trig- gering due to noise. 3 rt maximum on?time adjust. the rt pin establishes the ramp charging current. the pwm comparator es- tablishes the switch on time from the ramp and fb signal. pulling the rt pin below the disable threshold forces the controller in the armed mode where all switching functions cease. 4 gnd ground. this is the ground reference for the controller. all bypassing and control components should be connected to the gnd pin with a short trace length to minimize noise. 5 drv drive. the high current capability of the totem pole gate drive makes it suitable to directly control high gate charge power mosfets. the driver stage provides both passive and active pull?down circuits which force the mosfet gate off when vcc is below normal operating levels. 6 vcc ic supply. this is the positive supply of the controller and source for powering external circuits. internal bias will be disabled when external power is sufficient to maintain operation. 7 nc no?connect. this missing pin provides creepage distance. 8 hv high?voltage input. monitors input voltage for brown?out detection and power to operate controller.
ncl30060 www. onsemi.com 5 table 2. maximum ratings (notes 1, 2, 3 and 4) rating symbol value unit fb voltage v fb ?0.3 to 10 v fb current i fb 10 ma cs/zcd voltage v cs/zcd ?0.9 to 12.4 v cs/zcd current i cs/zcd ?2 / +5 ma rt voltage v rt ?0.3 to 5 v rt current i rt 10 ma drv voltage (note 2) v drv ?0.3 to v drv(high) v drv sink current i drv(sink) 400 ma drv source current i drv(source) 250 ma supply voltage v cc ?0.3 to 30 v supply voltage rate of change dv cc /dt 1 v/ s supply current i cc 20 ma hv voltage v hv ?0.3 to 700 v hv current i hv 20 ma thermal resistance, junction to ambient 1 oz cu printed circuit copper clad) r ja 125 c/w esd capability human body model per jedec standard jesd22?a114e. (note 5) machine model per jedec standard jesd22?a114e. charge device model per jedec standard jesd22?c101e. 5000 200 1500 v operating temperature range while biased t j ?40 to 105 c maximum junction temperature t jmax 150 c storage temperature range t stg ?60 to 150 c lead temperature (soldering, 10 s) t l 300 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. v cs/zcd(max) is the maximum voltage of the pin shown in the electrical table. when the voltage on this pin exceeds 7.4 v, the pin sinks a current equal to [(v cs/zcd ? 7.4 v) / 1 k ]. a v cs/zcd of 9 v generates a sink current of approximately 1.6 ma. 2. maximum driver voltage is limited by the driver clamp voltage, v drv(high) , when v cc exceeds the driver clamp voltage. otherwise, the maximum driver voltage is v cc . 3. this device contains latch?up protection and has been tested per jedec standard jesd78d, class i and exceeds 100 ma. 4. low conductivity board. as mounted on 80 x 100 x 1.5 mm fr4 substrate with a single layer of 50 mm 2 of 2 oz copper trances and heat spreading area. as specified for a jedec51?1 conductivity test pcb. test conditions were under natural convection of zero air f low. 5. pin 8 hv pin is esd rated to 1200 v.
ncl30060 www. onsemi.com 6 electrical characteristics (v cc = 14 v, v hv = 120 v, v fb = 4 v, v cs/zcd = 0 v, c drv = 1 nf, r t = 20 k , for typical values t j = 25 c, for min/max values, t j is ? 40 c to 105 c, unless otherwise noted) characteristic test conditions symbol min typ max unit startup and supply circuits supply voltage startup threshold minimum operating voltage operating hysteresis undervoltage lockout hysteresis between v cc(min) and v cc(uvlo) internal latch/logic reset level transition from i start1 to i start2 1 v/ms, v cc increasing 1 v/ms, v cc decreasing v cc(on) ? v cc(min) v cc decreasing 1 v/ms, v cc(min) ? v cc(uvlo) v cc decreasing v cc increasing v cc(on) v cc(min) v cc(hys1) v cc(uvlo) v cc(hys2) v cc(reset) v cc(inhibit) 11.75 10.7 0.9 8.2 2.0 4.5 0.35 12.5 11.5 ? 8.8 ? 5.5 0.7 13.75 12.8 ? 9.4 ? 7.5 0.95 v supply current in fault mode in disable modes active mode without c drv , f sw = 60 khz active mode with c drv , f sw = 60 khz v rt = 0 v c drv = open c drv = 1nf i cc1 i cc2 i cc4 i cc5 140 300 800 1490 190 335 870 1600 240 450 975 1700 a startup current v cc = 0 v to v inhibit v hv = 400v i start1 i start2 i start3 0.31 9 3.5 0.77 14 5.25 1.23 19 7.00 ma v cc overvoltage protection threshold v cc(ovp) 27 28 29 v v cc overvoltage protection delay t delay(vcc_ovp) 15 30 50 s startup circuit off?state leakage current v hv = 400 v, v cc = v cc(on) to v cc(max) i hv(off) ? 24 30 a minimum startup voltage i start2 = 1 ma v hv(min) ? ? 40 v startup current transition voltage threshold i start3 = 5.25 ma v hv(tran) 160 175 190 v gate drive rise time (10?90%) v drv from 10 to 90% of v drv t pdrv(rise) ? 80 180 ns fall time (90?10%) v drv from 90 to 10% of v drv t pdrv(fall) ? 40 80 ns current capability source sink v drv = 2 v v drv = 10 v i drv(src) i drv(snk) ? ? 250 400 ? ? ma high state voltage v cc = v cc(uvlo) + 0.2 v, r drv = 10 k v drv(highuvlo) ? ? 0.25 v v cc = v cc(ovp) ? 0.5 v , r drv = 10 k v drv(high) 10 12 14 v low state voltage i drv = 100 a v drv(low) ? ? 0.25 v feedback feedback open voltage v fb = open v fb(open) 6.0 6.3 6.6 v minimum fb voltage to generate drive pulses v fb decreasing v fb(offset) 0.60 0.70 0.80 v feedback bias resistor r fb(bias) 20 25.8 29.6 k constant on time generator on time r t = 20 k , v fb = v fb(open) r t = 10 k , v fb = v fb(open) r t = 80 k , v fb = v fb(open) r t = 80 k , v fb = 4.45 v r t = 80 k , v fb = 3.2 v t on1 t on2 t on3 t on4 t on5 4.75 2.37 18.4 13.6 9.0 5.0 2.50 19.5 14.5 9.56 5.25 2.63 20.7 15.5 10.1 s maximum on time r t = 110 k to open, v fb = v fb(open) t on(max) 22.0 27.5 33.0 s product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
ncl30060 www. onsemi.com 7 electrical characteristics (v cc = 14 v, v hv = 120 v, v fb = 4 v, v cs/zcd = 0 v, c drv = 1 nf, r t = 20 k , for typical values t j = 25 c, for min/max values, t j is ? 40 c to 105 c, unless otherwise noted) characteristic unit max typ min symbol test conditions constant on time generator maximum on?time feedback voltage v fb increasing v fb(tonmax) 5.415 5.70 5.985 v rt pin regulation voltage v rt(reg) ? 2.0 ? v on?time modulation frequency f mod 254 292 325 hz on time modulation t on(mod) 4 6 8 % disable function rt disable current threshold i rt decreasing i rt(disable) 250 325 400 a rt enable threshold v rt increasing v rt(enable) 380 400 420 mv rt pull?up current in disable mode i rt(dis) 45 50 55 a disable blanking i rt increasing or v disable decreasing t disable(blank) 6.8 8 9.8 s zero current detection zcd arming threshold v cs/zcd increasing v zcd(arm) 225 250 275 mv zcd trigger threshold v cs/zcd decreasing v zcd(trig) 35 55 90 mv zcd arming blanking duration t arm(blank) 1.7 2.05 2.35 s zcd propagation delay v cs/zcd stepping from 2.0 v to 0 v, dv/dt = 20 v/ s, v cs/zcd = v zcd(trig) to v drv = 10% t zcd(prop) ? 150 170 ns input voltage excursion upper clamp negative clamp v cc = 14v, i cs/zcd = 5 ma v cc = 14v, i cs/zcd = ?2 ma v cs/zcd(max) v cs/zcd(min) ? ?0.9 12.4 ?0.7 ? 0 v cs/zcd open voltage v zcd(open) 6.5 ? ? v pull?up current source i cs/zcd 0.7 1.0 1.3 a timeout after last demagnetization detection v cs/zcd > v ilim2 t off1 t off2 100 1000 200 1250 300 1700 s minimum zcd pulse width between v zcd(rising) and v zcd(falling) to drv t sync ? 70 200 ns current sense current sense voltage threshold t j = 25 c t j = ?40 c to 125 c v ilim1 242.5 238 250 250 257.5 262 mv propagation delay step v cs/zcd 0 v to v ilim1 + 0.1 v to drv falling edge, t ilim1 ? 100 200 ns leading edge blanking duration step v cs/zcd 0 v to v ilim1 + 0.1 v to drv falling edge, t cs(leb1) 250 325 400 ns abnormal overcurrent fault threshold v ilim2 475 500 525 mv fault propagation delay step v cs/zcd 0 v to v ilim2 + 0.1 v to drv falling edge, t ilim2 ? 125 175 ns fault leading edge blanking duration step v cs/zcd 0 v to v ilim2 + 0.1 v to drv falling edge, t cs(leb2) 90 120 150 ns leading edge blanking duration ratio t leb(leb2) /t leb1 t leb(ratio) ? 0.37 ? ? number of consecutive abnormal current events to enter fault mode (latch mode available on customer request) n ilim2 ? 4 ? product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
ncl30060 www. onsemi.com 8 electrical characteristics (v cc = 14 v, v hv = 120 v, v fb = 4 v, v cs/zcd = 0 v, c drv = 1 nf, r t = 20 k , for typical values t j = 25 c, for min/max values, t j is ? 40 c to 105 c, unless otherwise noted) characteristic unit max typ min symbol test conditions output short circuit and overvoltage protection output short off?time detector threshold (note 6) detected during drv low t off(os) 43 50 55 s output short detection integration weighting ratio (note 6) n intratio(os) = charging speed(output short detected) / discharging speed (normal operation) n intratio(os) 20 output short detection integration time for continuous integration pulses (note 6) t intcon(os) 36.7 40 45.7 ms overvoltage threshold drv is low v ovp 5.8 6.0 6.2 v overvoltage propagation delay v cs/zcd = 0 v to 7 v ramp, dv/dt = 1 v/ s, v cs/zcd = v ovp to drv low t ovp(prop) ? ? 2.5 s overvoltage blanking t ovp(blank) 1.5 2.0 2.5 s number of consecutive overvoltage events to enter fault mode mode (latch mode available on customer request) n ovp ? 4 ? auto?recovery timer duration t autorecovery 0.8 1.0 1.2 s brown?out protection (does not apply to b1 option) system startup threshold v bo(start) 102 111 120 v system shutdown threshold v bo(stop) 88 96 104 v brown?out detection blanking time v hv decreasing, delay from v bo(stop) to drive disable t bo(stop) 43 54 65 ms thermal protection thermal shutdown temperature increasing t shdn ? 160 ? c thermal shutdown hysteresis temperature decreasing t shdn(hys) ? 50 ? c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 6. parameter does not apply to b2 option.
ncl30060 www. onsemi.com 9 detailed operating description high voltage startup circuit the ncl30060 integrates a 700 v startup regulator eliminating the need of external startup components. the startup regulator consists of a constant current source that supplies current from the high voltage input terminal (hv) to the supply capacitor on the vcc pin (c cc ). the startup circuit current (i start2 ) and (i start3 ) are disabled if the vcc pin is below v cc(inhibit) . in this condition, the startup current is reduced to i start1 , typically 0.77 ma. in addition, this regulator reduces no load power and increases the system efficiency as it uses negligible power in the normal operation mode. after vcc pin is higher than v cc(inhibit) threshold, the startup circuit uses i start3 to charge the v cc capacitor during the initial charging. i start3 has a typical value of 5.25 ma. once c cc is charged to the startup threshold, v cc(on) , typically 12.5 v, the startup regulator is disabled and the controller is enabled. the initial charging on v cc capacitor is done. the controller is then biased by the v cc capacitor. figure 3. initial charging of v cc and normal dss the startup regulator is enabled once v cc falls below its minimum operating threshold, v cc(min) , typically 11.5 v. the driver continues operation while v cc is charged by the startup circuit. this operating mode is known as dynamic self supply or dss. during normal dss operation, the startup circuit uses i start2 to charge the v cc capacitor when the line voltage is below v hv(tran) , and the startup circuit uses i start3 when the line voltage is higher than v hv(tran) . v hv(tran) has a typical value of 175 v. figure 3 shows the initial charging of v cc capacitor and normal dss. the startup circuit continues to charge v cc until the convertor bias winding is able to provide power to the v cc capacitor. as long as the bias winding can maintain the v cc voltage higher than v cc(min) , the startup circuit will not be enabled. the startup circuit enters dss mode if the v cc voltage is lower than v cc(min) . the increase in current consumption due to external gate charge is calculated using equation 1. i cc(gate charge) f q g (eq. 1) where f is the operating frequency and q g is the gate charge of the external mosfets. the additional gate charge current should not exceed the startup circuit. otherwise, v cc will not charge to v cc(on) and may stay at an undetermined voltage while dissipating excessive power. the controller and the startup circuit are disabled if the junction temperature of the device exceeds the thermal shutdown threshold, t shdn , typically 160 c. the controller is disabled if v cc falls below the undervoltage lockout (uvlo) threshold, vcc (uvlo) , typically 8.8 v. a noise filter, t uvlo , 25 s maximum, blanks the uvlo fault before disabling the controller. feedback input a signal proportional to the output error is applied to the fb pin by means of an optocoupler or other means such as an op amp. the pwm comparator compares the feedback or error signal to a level shifted voltage ramp to control the power switch on?time. the feedback voltage is directly proportional to the output power. an internal pull up resistor, r fb , drives this pin to provide more linear response from the optocoupler transistor. the voltage reference biasing r fb is typically 6.3 v . the minimum on?time, t on(min) , is determined by the propagation delay of the pwm comparator and control logic. it is limited below 200 ns. the minimum on?time is achieved when v fb is right on the voltage offset of the on?time ramp, v fb(offset) . a v fb below v fb(offset) results in no drive pulses or ?zero? on?time. the maximum on?time is limited by the maximum on?time comparator. the comparator is enabled once the feedback voltage, v fb , exceeds v fb(tonmax) . this establishes the point where the led driver transitions from constant current feedback (if so configured) to primary power control. maximum on?time the pwm comparator controls the on?time by comparing an internal voltage ramp, v on?time , to the feedback voltage. the internal ramp is generated by charging an internal capacitor with a fixed current source. the slope of the ramp is adjusted by the user using an external timing resistor, r t , between the r t and gnd pins. the architecture of the on?time control circuitry is shown in figure 4.
ncl30060 www. onsemi.com 10 figure 4. on?time control architecture pwm comparator max on time comparator rt current mirror ? + on time ramp drv fb offset ramp modulation gnd r s q q uvlo clamp drv fb active rt enable comparator + ? active active max on?time clamp drv rt disable comparator + ? reset dominant latch delay t disable(blank) / t enable(blank) i rt(disable) * r cs v rt(enable) v prt t on(mod) f mod r cs v cc i rt v on?time v ton(max) v dd2 the on?time is internally modulated to reduce the emi signature of the controller. the modulation is accomplished by modulating the charge current using an internal triangle wave oscillator. the char ge current is adjusted 6% from the nominal value. the emi signature of the controller is spread over a wide range of frequencies eliminating high peaks during an average reading. the absolute maximum on?time determines the maximum power of the system. the ncl30060 accurately controls the maximum on?time of the system by the max on?time clamp circuits. it ensures that on?time can?t exceed t on(max) , typically 27.5 s, when the r t resister value is above 110 k . there is also a fixed voltage reference, v ton(max) , which defines the maximum ef fective v fb voltage. given a certain r t value between 10 k and 110 k , the maximum on?time comparator controls the on?time when primary side regulation is required. this could occur during an overload condition or during startup when the feedback signal is not present. the relationship between r t and t on(max) is given by equation 2 and figure 5. t on(max) 0.25 r t (eq. 2) where t on(max) is in s and r t is in k . figure 5. maximum on?time vs r t the rt pin has a threshold output current of i rt(disable) which has a maximum value of 400 a. the maximum on?time is limited to 27.5 s if the pin is left open or the rt is higher than 110 k . if the resistance between rt pin and gnd is small enough to make the rt pin current higher than i rt(disable) , the device is disabled after the blanking delay t disable(blank) and the rt pin output current is switched to
ncl30060 www. onsemi.com 11 i rt(dis) which has 50 a typical value. after the device is disabled, the integrated hv source maintains v cc above v cc(min) . the ic is activated when the voltage of the rt pin is higher than the v rt(enable) , which has typical value of 400 mv. and the rt pin output current is switched back to normal operation, and the rt voltage is regulated to v rt(reg) ,which has a typical value of 2 v. the timing resistor should be placed as close as possible to the rt and gnd pins with short trace lengths. care should be taken to keep switching nodes (high dv/dt) away from r t to reduce noise pickup. current sense, zero current and overvoltage detection the ncl30060 uses a novel architecture combining the current sense, the zero current detector (zcd), output overvoltage and shorted output detector functions in a single terminal. figure 6 shows the circuit schematic of the current sense and zcd detectors. figure 6. current sense and zcd detectors schematic short winding comparator + ? cs/zcd peak current comparator zcd comparator disable drv reset uvlo edge detector zcd blanking time + ? + ? selector ilim2, ovp gnd r s q q uvlo clamp drv tshdn counter reset count active ilim2 re?start edge detector drv hv(high) drv drv reset dominant latch t off1,2 timer v ilim1 v ilim2 v zcd v cc v cc leb t cs(leb1) leb t cs(leb2) v cc current sense the switch current is sensed across a sense resistor, r sense , and the resulting voltage ramp is applied to the cs/zcd pin. the current signal is blanked by a leading edge blanking (leb) circuit. the blanking period eliminates the leading edge spike and high frequency noise during the switch turn?on event. the leb period, t cs(leb1) , is typically 325 ns. the current limit comparator disables the driver once the current sense signal exceeds the current sense reference, v ilim1 , typically 0.25 v. the next switching cycle is initiated by the zcd or watchdog timer. a severe overload fault like a secondary side winding short circuit causes the switch current to increase very rapidly during the on?time. the current sense signal significantly exceeds v ilim1 . but, because the current sense signal is blanked by the leb circuit during the switch turn on, the current could damage the system. the ncl30060 protects against this fault by adding an additional comparator, short circuit comparator. the current sense signal is blanked with a shorter leb duration, t cs(leb2) , typically 125 ns, before applying it to the short circuit comparator. the voltage threshold of the comparator, v ilim2 , typically 0.5 v, is set twice the level of v ilim1 , to avoid interference with normal operation. four consecutive faults detected by the short circuit comparator causes the controller to enter a fault mode. the ncl30060b will auto?recover from the fault state if the short is removed. the count to 4 provides noise immunity during surge testing. the counter is reset each time a drv pulse occurs without activating the short circuit comparator. the watchdog timer duration (t off2 ) is increased to 1.25 ms independent of the pfc zcd state.
ncl30060 www. onsemi.com 12 figure 7. secondary side winding short?circuit waveforms figure 7 shows simulation results for an output winding short. the simulation waveforms are described below: ? drv/v is gate drive signal for the pfc switch. ? vcs/v is the signal on the cs/zcd pin. ? zcdw/v is the voltage across the zcd winding. ? vhv1/v is the voltage on the hv pin. the converter is operating normally and a momentary fault is applied at 24 ms. once the fault is applied, the watchdog timer duration increases to t off2 . the fault is removed after two faults overcurrent events are detected. the fault is re?applied at 35 ms. after four consecutive overcurrent conditions are detected, the fault signal goes high. zero current detection the off?time in a crm topology varies with the instantaneous line voltage and it is adjusted every cycle to allow the inductor current to reach zero before the next switch cycle begins. the inductor is demagnetized once its current reaches zero. once the inductor is demagnetized the drain voltage of the switch begins to fall. the inductor demagnetization is detected by sensing the voltage across the inductor using an auxiliary winding. this winding is commonly known as a zero crossing detector (zcd) winding. this winding provides a scaled version of the drain voltage. figure 8 shows the zcd winding arrangement. dzcd rcs rzcd rsense cs/zcd drv switch figure 8. zcd winding implementation the zcd voltage, v cs/zcd , is positive while the switch is off and current flows on the secondary side. v cs/zcd drops to and rings around zero volts once the transformer is demagnetized. the next switch cycle commences once a negative going transition is detected in the cs/zcd pin. a positive transition (corresponding to the switch turn off) arms the zcd detector to prevent false triggering. the arming of the zcd detector, v zcd(arm) , is typically 250 mv (v cs/zcd increasing). the trigger threshold, v zcd(trig) , is typically 55 mv (v cs/zcd decreasing).
ncl30060 www. onsemi.com 13 the ncl30060 incorporates a minimum of f?time delay, t arm(blank) .,typically 2.0 s . this delay blanks the ringing which may be present on the bias winding during start up or if the output of the converter is shorted. the next drv pulse is initiated once t arm(blank) expires if a zcd transition is detected prior to the delay expiring. otherwise, it will initiate on the zcd transition after t arm(blank) expires. in the absence of a zcd transition, the watchdog timer initiates the next drive pulse. the cs/zcd pin is internally clamped to v cc thru an internal diode. a 7.4 v zener diode with a 1 k resistor to gnd also clamp the pin. a resistor in series with the cs/zcd pin is required to limit the current into pin. the zener diode also prevents the voltage from going below ground. figure 9 shows typical zcd waveforms. figure 9. zcd winding waveforms during startup there are no zcd transitions to set the pwm latch and generate a drv pulse. a watchdog timer, t off1 , starts the drive pulses in the absence of zcd transitions. its duration is typically 200 s. the timer is also useful during startup and while operating at light load because the amplitude of the zcd signal may be very small to cross the zcd thresholds. the watchdog timer is reset at the beginning of a drive pulse. it is disabled if the cs/zcd pin is above the zcd arming threshold. the watchdog timer duration increases to t off2 , typically 1.25 ms, when a v ilim2 fault is detected. overvoltage protection output overvoltage protection (ovp) is provided by monitoring the cs/zcd pin during the off?time. a dedicated comparator compares the voltage on cs/zcd pin to an internal reference, v ovp , typically 6 v. if 4 consecutive ovp events are detected the controller enters a fault mode. a 2 s blanking delay, t ovp(blank) , blanks the signal cs/zcd signal after the drive turns off to blank ringing generated by system parasitics. the blanking provides protection during power up and steady state operation. figure 10 shows the controller shutting down after an overvoltage condition is detected. figure 10. overvoltage detection operating waveforms output short circuit detection when the converter is operating with low output voltage, the off?time is extended in crm operation. in figure 11 of the output short detection function block, the maximum off?time detector signals when the off time is longer than 50 s. this 50 s off time detection triggers a 150 s pulse to feed the integrator. the integrator has a weighted integration feature, which makes the charging 20 times faster than the discharging. a continuous stream of 150 s pulses will reach the integrator threshold in 40ms. periods of time without triggering the 150 s timer will extend the time to reach the threshold. the integrator dischar ges as the relative number of 150 s pulses over time decreases. figure 11. output short?circuit detector when the threshold is reached, the system will determine there is an output short event. the system enters into fault mode. the ncl30060b will try to auto?recover after a 1 sec typical delay. this minimizes system power consumption due to the output short event. figure 12 shows auto?restart operating waveforms.
ncl30060 www. onsemi.com 14 figure 12. output short detection and protection waveform version ncl30060b2 is intended for constant voltage (cv) regulated output drivers where a dc?dc converter or linear regulator in the second stage controls the current to the leds so the output short circuit protection detector function has been disabled. brown out detection the ncl30060 includes brown out protection providing a defined shutdown for low input voltage. this feature is enabled after a v cc reset event and does not allow the controller to enter active mode until the input voltage is above the startup threshold, typically 111 v. if the input voltage remains below the system shutdown threshold, typically 96 v, longer than the brown out detection blanking time, typically 54 ms, a shutdown flag is set. gate drive pulses will continue to be issued until the input voltage is near the ac line voltage zero crossing. when a zero crossing is detected and the flag is set, gate drive pulses cease thereby stopping power delivery to the led load. the brown out flag remains set and switching is suspended until the input voltage rises above the startup threshold. delaying termination of gate drive pulses until the zero crossing ensures the system is at a low power state before shutting down. this approach avoids a situation where energy stored in the input filter may artificially force the sensed voltage to cross the startup threshold if switching is abruptly terminated. a false startup level would be followed by crossing the shutdown threshold again. such cycling on and off near the brown out threshold would result in led flicker. allowing the energy to discharge naturally near the zero crossing provides a clean brown out shutdown. mosfet driver the ncl30060 maximum supply voltage, v cc(ovp) , is 28 v. typical high voltage mosfets have a maximum gate voltage rating of 20 v. the driver incorporates an active voltage clamp to limit the gate voltage on the external mosfet. the voltage clamp, v drv(high) , is typically 12 v with a maximum limit of 14 v. auto?recovery the controller is disabled and enters a fault mode if v cc drops below v cc(uvlo) or a non?latching fault is detected. the controller auto?restarts after the auto?recovery timer t autorecovery , expires, typically 1 s. thermal shutdown an internal thermal shutdown circuit monitors the junction temperature of the ic. the controller including the startup circuit is disabled if the junction temperature exceeds the thermal shutdown threshold, t shdn , typically 150 c. once a thermal shutdown condition is validated, the startup circuit is disabled. the startup circuit is enabled once v cc falls below v cc(reset) , charging v cc up to v cc(on) . the controller remains disabled if the thermal shutdown is present upon reaching v cc(on) . the controller restarts at the next v cc(on) once the ic temperature drops below t shdn by the thermal shutdown hysteresis, t shdn(hys) , typically 40 c. layout considerations the gnd pin is the reference point for the controller. unless specified otherwise, all measurements are made relative to this pin. both power and control circuits use this reference. it is recommended to have short traces between this pin and control components to reduce parasitic inductance. ordering information ordering part no. ocp brown out output short detection package shipping ? ncl30060adr2g* latched enabled enabled soic?7 (pb?free) 2500 / tape & reel NCL30060BDR2G auto?recoverable enabled enabled ncl30060b1dr2g* auto?recoverable disabled enabled ncl30060b2dr2g auto?recoverable enabled disabled ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *version available only by customer request.
ncl30060 www. onsemi.com 15 package dimensions soic?7 case 751u issue e seating plane 1 4 5 8 r j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b are datums and t is a datum surface. 4. dimension a and b do not include mold protrusion. 5. maximum mold protrusion 0.15 (0.006) per side. s d h c dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?a? ?b? g m b m 0.25 (0.010) ?t? b m 0.25 (0.010) t s a s m 7 pl 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncl30060/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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